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51.11.2.5.6 Plating Voids. When found in the microsection, plating voids should be limited to one per microsection. No void should span more than 5 percent of the PCB thickness or be present at the interface of internal copper foil to the plating. 51.11.2.5.7 Solder Resist Thickness. When the procurement documentation specifies this thickness, it should be measured at the thinnest area observed between the copper and the surface of the solder resist. This is usually at the corner of the copper trace. 51.11.2.5.8 Wicking. During the drilling and hole cleaning process, glass fibers from the base material can be removed inward from the hole surface. During the copper-plating process, the copper will follow this glass removal topography, creating pockets of plating that extend laterally from the hole into the base material. This wicking can significantly reduce the electrical conductor spacing between holes or between holes and internal circuits. The maximum allowances for wicking can be found in IPC-A-600. (see Fig. 51.29). 51.11.2.5.9 Interconnection Separation. This is defined as the separation between the internal copper foil and the copper plating in the hole. It is also sometimes referred to as post separation.Any evidence of this imperfection in the FIGURE 51.29 Wicking, vermicrosection makes the associated PCBs nonconforming. This imperfection is a tical microsection (Courtesy of IPC.) severe issue that will likely reduce the service life of the PCB (see Fig. 51.30).

FIGURE 51.30 Interconnection separation, vertical microsection. (Courtesy of Microtek Laboratories.)

The major concept that has to be addressed is assigning the various parallel tasks to the eight processors in an intelligent fashion This can be done in two ways In the first, we write a program just as we would for a one-processor linear system, and the computer is so smart that it figures what has to be done and how it is to be done in a multiprocessor system The second method involves the programmer breaking the task down into well-thought-out subtasks and then assigning the subtasks to the eight processors, as appropriate Because each cog is capable of doing more than one thing, the problem lends itself to elegant and innovative solutions As things stand as of this writing, the artificial intelligence needed to allow the computer to assign the tasks autonomously does not exist for the Propeller.

51.11.2.5.10 Material Fill of Blind and Buried Vias. When blind or buried vias are present in a PCB, it is important that they be microsectioned and evaluated in addition to any through holes evaluated. Buried vias are typically filled with resin, and this resin should fill a minimum of 60 percent of each buried via.

Reliability inspection consists of performing specific tests to ensure that the PCB will function under the influence of the climatic and/or mechanical forces to which it will be subjected during use Environmental tests are performed on preproduction PCBs or specifically designed test coupons to verify design adequacy and manufacturing process control Specific tests are sometimes specified as part of the PCB acceptance procedure to expose a prospective failure situation Specific environmental testing, as part of the acceptance procedure, is prevalent in high-reliability programs Note that it is recommended that a simulation of the cycles required for component assembly and rework be performed as a preconditioning prior to environmental exposure Test results then relate to the actual condition of the PCB after assembly Specific test methods for performing these tests can be found in IPC-TM-650 5112.

12:

1 Thermal Shock The thermal shock test is particularly efficient in identifying (1) PCB designs with areas of high mechanical stress and (2) the resistance of the PCB to exposure of high- and lowtemperature extremes This test is periodically required in IPC-6012 for product acceptance and is also used for PCB supplier qualification inspection A thermal shock is induced on a PCB by exposure to severe and rapid differences in temperature The test is usually performed by transferring the PCB from one temperature extreme (eg, 125 C) to the other (eg, 55 C) rapidly, usually in less than 2 minA resistance difference in excess of 10 percent between the 1st and 100th cycles is considered nonconforming, but requirements in the thousands of cycles are sometimes specified for high-reliability PCBs.

The thermal shock test can produce cracking of plating in the holes and base material de-lamination (refer to IPC-TM-650, method 2672, for the procedure) Note that continuous electrical monitoring during thermal shock cycling will detect intermittent electrical circuits that may not be detected with periodic measurement techniques Intermittent circuits usually occur at the high-temperature extreme..

FIGURE 51.31 Laboratories.)

We have to resign ourselves to assigning the tasks to the various subprocessors individually as we design the application..

Surface Insulation Resistance (SIR) SIR testing evaluates the electrical resistance between two surface electrical conductors separated by dielectric material. This test detects the bulk conductivity and electrical leakage through surface electrolytic contaminants when the samples are exposed to a high-humidity environment. The test conditions are a relative humidity of 85 to 92 percent at a temperature range of 35 to 45 C without the use of an electrical forcing potential. (See Fig. 51.31 for example of a SIR test pattern.)