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FIGURE 54.6 Interconnect testing drives unique patterns assigned to each node from drivers to receivers. In this case, a short is shown that creates a wire OR result.

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important one. It signifies that the standard anticipates being used as a standardized protocol for accessing any on-chip, board-level, or system-level testability scheme. In support of this, the standard is deliberately extensible, allowing clever designers to implement additional operational modes that can be used to solve unique testing problems. The 1149.1 standard has proven itself to be quite useful and it has several contributions. First, it allows the creation of software that can automatically write tests for boards where in the past the same level of test effectiveness was nearly impossible to achieve, and then only with weeks or even months of skilled labor. It is not uncommon to see a boundary scan board test prepared in a single day that otherwise might have taken weeks. Second, 1149.1 ICs can read their input pins and scan out the result. This allows diagnostic software to pinpoint the location of open solder problems where in the past an IC might have been falsely indicted as faulty. Third, it allows tests to be performed on digital circuits without 100 percent accessibility to board nodes. With the trend toward miniaturization of components making it difficult to provide full nodal access, boundary scan is allowing the elimination of many access points. Of course, not all points may be eliminated, so one must understand which are still necessary. Finally, because many industry segments are affected by the test problem, a standard offers a way for everyone to benefit. One can find a large number of applications and tools available to solve testing problems that would not have been possible without a standard.

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IEEE 1149.4, Boundary-Scan for Mixed-Signal Circuits Boundary scan (1149.1) is a digital testability standard. However, there is also a trend in the superintegration of circuitry toward higher mixed-signal digital-analog content in our designs. The IEEE has developed a mixed-signal testability bus with a new standard 1149.4.4 6

This standard is constructed as a superset of 1149.1 boundary scan, adding two additional analog test pins to the definition. The goal of the standard is to support opens and shorts testing of mixed-signal boards and to provide the capability of making analog value measurements of discrete analog components such as resistors, inductors, and capacitors without direct nodal accessibility, that is, a full bed of nails. (See Fig. 54.7.) It has been likened to in-circuit testing without a bed of nails, which is again not without caveats. (The elimination of test access points will still have to be done with thoughtful deliberation.)

FIGURE 54.7 A mixed-signal circuit with some possible defects. IC pins marked A and D are analog and digital, respectively.

Pos[3] stack2[25] stack3[25] stack4[25] stack5[25] Pulswidth PresPosition initPosition TargetPosition PositionError MinGain Gain MaxGain Index Integ PotOne

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A mixed-signal device constructed with 11494 has the general architecture shown in Fig 548 It is in many ways identical to an 11491 IC, but it has an additional analog test access port (ATAP) that is used to facilitate the control and observability of analog signals at device pins The ATAP brings into the IC two additional analog signals that are used during testing With 11494, digital device pins are treated exactly as done with an 11491 boundary register Analog pins have an augmented structure called an analog boundary module (ABM) as part of the boundary register The ABM allows an analog pin to be tested for simple shorts and opens (this is called 11491 interconnect test emulation) as well as allowing the injection and/or observation of analog signals via the ATAP An ATE system can utilize the test resources in an 1149.

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