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You need to indicate to which control flow in the calling task flow control should be returned. To do so, set the Outcome Name property of the task flow return to a control flow on the calling task flow.

One can think of the I/O pins of the device being connected to shift register cells; states can be shifted in that will finally appear on all output pins (control) and the states of all input pins can be captured and shifted out (observe) This gives 11491cognizant software a powerful tool for controlling and/or observing board-level node states Figure 543 shows a simplified overview of the architecture Boundary register cells interposed between the IC pins and the internal logic surround the normal content of the IC called the mission logic A small state machine called the test access port (TAP) is used to control the test functions Four mandatory test pins (test clock [TCK], test mode select [TMS], test data in [TDI], and test data out [TDO]) give standardized access to the test functions All 1149.

1 devices have a 1-bit BYPASS register used to bypass the (much longer) boundary register if it is not needed in a given testing activity Figure 543 also shows an optional IDCODE register that can be shifted out to uniquely identify the IC, its manufacturer, and its revision It is intended that collections of ICs (called chains, as shown in Fig 544) with 11491 be connected TDO-to-TDI so that they may form a long, shiftable register structureThe primary use for the 11491 EXTEST capability is to conduct board-level tests for shorts and opens This is an example of how resources included in an IC design may be used to help with the testing problem at other levels in the manufacturing process Briefly, interconnections between ICs are tested as follows Consider the circuitry in Fig 545.

Some circuit nodes (also known as nets or traces) are accessible with a bed of nails and some are not (To avoid clutter, the TCK and TMS signals are not shown) Boundary scan can be used to test all the nodes; those with nails can be tested by coordinating nails with boundary scan resources and those without nails are tested solely with boundary scan..

Motor Position Controlled by a Potentiometer (continued)

* An IEEE standard has as a suffix the year of its creation or last update. A standard must be updated and/or reaffirmed every 5 years. Up to two supplements to a standard may be issued within the 5-year cycle. Users of a standard should keep up to date with it. Bidirectional signal pins can both observe and control the nodes to which they are connected. An optional fifth pin called Test Reset (TRST*) is an asynchronous active low reset for the 1149.1 circuitry. Because any TAP can be reset by five clock pulses to TCK while TMS is held high, TRST* is not actually needed for resetting an 1149.1 device. It is often included as a fail-safe measure with a board-level pull-down resistor providing a constant reset to the TAP. Many 1149.1-compliant ICs do not include the TRST* pin because the extra pin required may be too costly.

As an example of this, boundary scan can be used to supply test patterns to nodes through a serialization process that a human would find laborious, but that is simple for a computer. When a set of patterns has been delivered (to control) and monitored (to observe) by the appropriate boundary register cells, we have uniquely identified each node with a signature. A defect such as a short will cause two nodes to have deviant signatures, as shown in Fig. 54.6. Software can correlate observed deviations with the known boundary scan structure of each IC and the board netlist to yield a diagnostic message.

FIGURE 54.4 A collection (chain) of boundary scan devices can be used to test interconnections between ICs.

FIGURE 54.5 A set of boundary scan ICs with interconnections. Note that four nodes do not have bed-of-nail access.

13:

The EXTEST capability can also be used during system testing to see if there are any system integration problems such as bad connections in backplanes and cabling. An IC designer may not see much attraction in EXTEST, but the 1149.1 standard offers other test modes that will allow a designer to access internal scan paths or built-in self-test functions. The 1149.1 standard s name has two parts, Standard Test Access Port being the first and crucially

'The system clock spec 'set this to 0 to reverse a runaway motor 'set to 1 for normal operations. 'You can also fix this runaway by reversing 'encoder leads.