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Internally Observable Imperfections These are imperfections where evaluation from the outside of the PCB is not possible. They require the preparation of a microsection in order to view and evaluate conformance. Preparing a microsection of the PCB requires a great deal of skill. The method of sample removal, the microsection materials used, and the grinding/polishing techniques all significantly affect

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FIGURE 51.17 Impedance diagram of a PCB. (Courtesy of Microtek Laboratories.)

the ability to produce a microsection that will reveal and not hide imperfections. The basic methodology for the preparation of microsections can be found in IPC Test Method 2.1.1, but numerous papers and articles have been written on the art of the microsectional preparation process. The use of test coupons to perform microsections is optimal due to the fact that internal layer connections do not always appear for every layer in holes on the PCB, whereas they always appear in a properly designed microsection test coupon. See Fig. 51.18 for a microsection of a multilayer PTH.

The system clock coordinates the operation of all the hardware items in an orderly fashion. The system clock rate can be controlled by the Propeller chip (although none of the programs in this book use that capability). The resister/capacitor combinations internal to the system allow the system clock rate to be used without an external crystal. It is also possible to use an external crystal to set the clock rate and use a multiplier to

FIGURE 51.18 Vertical PTH microsection of a multilayer PCB. (Courtesy of Microtek Laboratories.)

51.11.2.1 Microsectioning. Samples for microsectioning are removed from the PCB or test coupon.The removed specimen should contain at least three of the smallest holes in a line that will allow microsectioning. Because shearing of microsection samples from a PCB or coupon can result in creating failure mechanisms that are not truly present in the production PCB, the practice is not recommended. Routing or sawing microsection samples is the preferred method for sample removal. The samples should be mounted in a resin-based medium that does not produce too much heat during curing and does not shrink away from the surface of the holes being evaluated. Holes should be fully filled, as partially or nonfilled holes result in poor mount conditions, difficult sanding/polishing processes, and possibly erroneous thickness results. Examination under a microscope for internally observable attributes should be performed at 100 magnification. If it is not possible to determine whether the condition is acceptable, progressively higher magnifications should be used until accurate determination of acceptance is determined. Polishing vertical PTH cross sections to the center of the hole +/ 10 percent is critical. If the hole is polished less than or more than the center of the hole, the measured plating thickness will be artificially high. Horizontal plane, PTH cross sections are recommended as references for internal-layer interconnection quality and are prepared by grinding from the top down through the hole to the inspection area. See Fig. 51.19 for an example of a horizontal microsection.

FIGURE 51.19 Example of interconnection separation in a horizontal microsection. (Courtesy of Microtek Laboratories.)

Although horizontal PTH cross sections are usually more accurate for plating thickness, interconnection separation, and annular ring measurements, they do not allow adequate inspection of other attributes such as voids, plating uniformity, adhesion, etchback, and nodules. Surface plating thickness measurements are taken from vertical cross sections of conductor areas. Microsection mounts are usually etched with an appropriate etchant to show grain boundaries between the copper-clad foil and copper plating and to remove copper smearing introduced during the polishing process. 51.11.2.1.1 Thermal Stress Solder Float Test. Soldering temperatures expose PCBs to thermal and mechanical stress and may deform the PCB shape and cause premature degradation of the base material. Thermal stress inspection is performed to predict the acceptability of the PCBs after the assembly and rework process. PTH degradation, separation of platings or conductors, and base material delamination are induced or amplified by the thermal stress test. The PCB specimen is oven-conditioned to reduce moisture, placed in a dessicator on a ceramic plate to cool, fluxed, floated in a solder bath, and placed on an insulator to cool. Visual inspection for imperfections is followed by microsectioning of the PTHs and inspection under a microscope for integrity. Test coupons are typically used for thermal stress inspection.

51.11.2.2 Microsection Evaluation. The evaluation of internally observable attributes in the microsection consists of the following set of inspections: